The present invention relates to memory circuits.
Programmable logic devices (“PLDs”) (also sometimes referred to as complex PLDs (“CPLDs”), programmable array logic (“PALs”), programmable logic arrays (“PLAs”), field PLAs (“FPLAs”), erasable PLDs (“EPLDs”), electrically erasable PLDs (“EEPLDs”), logic cell arrays (“LCAs”), field programmable gate arrays (“FPGAs”), or by other names), are well-known integrated circuits that provide the advantages of fixed integrated circuits with the flexibility of custom integrated circuits. Such devices typically provide an “off the shelf” device having at least a portion that can be programmed to meet a user's specific needs. Application specific integrated circuits (“ASICs”) have traditionally been fixed integrated circuits. However, it is possible to provide an ASIC that has a portion or portions that are programmable. Thus, it is possible for an integrated circuit device to have qualities of both an ASIC and a PLD. The term PLD as used herein will be considered broad enough to include such devices.
PLDs have configuration elements that may be programmed or reprogrammed. Configuration elements may be realized as random access memory (“RAM”) bits, flip-flops, electronically erasable programmable read-only memory (“EEPROM”) cells, or other memory elements. Placing new data into the configuration elements programs or reprograms the PLD's logic functions and associated routing pathways. Configuration elements that are field programmable are often implemented as RAM cells (sometimes referred to a “configuration RAM” (“CRAM”)). However, many types of configurable elements may be used including static or dynamic RAM (“SRAM” or “DRAM”), electrically erasable read-only memory (“EEROM”), flash, fuse, and anti-fuse programmable connections. The programming of configuration elements could also be implemented through mask programming during fabrication of the device. While mask programming may have disadvantages relative to some of the field programmable options already listed, it may be useful in certain high volume applications. For purposes herein, the generic term “configuration element” will be used to refer to any programmable element that may be configured to determine functions implemented by other PLD elements.
In the typical FPGA embedded memory application, only read or write is performed on the same memory address (i.e., memory cell) during one clock cycle. Read can read the data value at the address location. Write can write new data into the address location. If the user wants to read the data value from the current address location, then write the new data into the same address location, two clock cycles are needed.
In order to support reading the old data then writing the new data to the same address location in one clock cycle, the bitlines need to be pre-charged to the supply voltage twice during the clock cycle. The first time, they are pre-charged to the supply voltage before the read operation. The second time, they are pre-charged to the supply voltage between the read operation and the write operation. Thus, once the read operation is completed, the bitlines are again pre-charged to the supply voltage and thereafter the write operation is performed.
Performing two pre-charge operations consumes additional power, involves additional design complexity, and increases the time required for the read/write operations.